how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
7 次查看(过去 30 天)
显示 更早的评论
Hello, I am working on generating a bitfile from a Simulink model. While converting, the Simulink model is using more slice LUTs (352,424 out of 203,800) and it is showing a utilization error. Is there any HDL configuration to reduce slice LUTs (such as using pipelining processes)?
My target device is PXIe-7858R.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1719906/image.jpeg)
0 个评论
采纳的回答
Kiran Kintali
2024-6-21
You may find these links helpful to reduce your area consumption on the hardware.
0 个评论
更多回答(0 个)
另请参阅
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!