I am assuming you are using an evaluation FPGA board.
Use traceability report to understand the elements of the generated code and relationship with the model elements.
You may want to follow the step by step workflow to get the code running on the hardware (FPGA/SoC) using this workflow.
HDL Coder Workflow Advisor (launched from HDL Coder toolstrip) helps you with the next steps after generaitng HDL.
Here are some additional references to download and readup for the next steps of FPGA/SoC workflow.
