How to generate Generic VHDL from simulink for sysgen model?

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Keththura
Keththura 2024-8-2
评论： Keththura 2024-8-2
I have used xilinx basic blocks to design a model. I wanted to generate generic VHDL without xilinx specific references. Eventhough i have choosen Behavioural HDL for implementation generated vhdl consist of xilinx specific DFlip-Flop and SRLUTs. Kindly let me know if there is a way? if the option is not being applied then how can we write a matlab sript to set automatically without doing it manually?

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回答（3 个）

Kiran Kintali
Kiran Kintali 2024-8-2
编辑：Kiran Kintali 2024-8-2
HDL Coder by default generates generic RTL. The RTL is vendor independent but target optimized. The generated RTL can be taken to any FPGA/SoC or an ASIC.
Can you let us know what you mean by Xilinx specific RTL. There is only one instance when you request use of the Floating Point library for Xilinx you would see any Xilinx specific floating point library primitives.
Please share a sample model for reference.
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Keththura
Keththura 2024-8-2
Thanks for your promt response.
My model has xilinx adders and delay units. Its is designed to support with xilinx FPGA. As the second use case i wanted to generete VHDL and do the synthesis with ASIC tools. When i use Sysgen token to generate VHDL the generated VHDL has three references to Xilinx components mentioned multiple times throughout the VHDL they are “FDE”, “fdse” & “SRLC32”.
These are denoting D-flipflops and 32 clock cycle - variable length Shift register LUT with clock enabled. They are not supported in the Synthesis.
Is there a way to generate generic VHDL without these xilinx references
Kiran Kintali
Kiran Kintali 2024-8-2
Can you confirm you use HDL Coder? https://www.mathworks.com/products/hdl-coder.html
Try these commands and check the synthesizable generated code
>> sfir_fixed
>> makehdl('sfir_fixed/symmetric_fir')

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Keththura
Keththura 2024-8-2
Keththura
Keththura 2024-8-2
I had tried from sysgen token to generate then it is succesfully generated but had those xilinx references. when i use simulink HDL coder then getting these error messages.
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Keththura
Keththura 2024-8-2
Normally i heard that if we select the behavioural HDL options in the xilinx blocks it will generate a generic VHDL that can be support for ASIC synthesis. But dont know the exact steps. Is there a way i could not able to design it using simulink blocks since i am using fixed point input formate.

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