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zcu102: split tasks between the 4 available CPUs

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TuttoAlDoc
TuttoAlDoc 2024-8-8，12:37
编辑： Kiran Kintali 2024-8-24，2:47
Hi,
I'm doing some testing on a ZCU102. I followed a few examples and I was able to run HDL to split some programming between FPGA and CPU and run my model on the target. Based on the examples I found, as far as I understand, basically everything that is not processed via HDL goes on the CPU. The ZCU102 as a quadcore. I would like to try to split some tasks between them. I found a few examples like but when I go into Allow tasks to execute concurrently on target and I click Configure Tasks I cannot find the ZCU102 in the possible target applications and if I select custom it just shows one CPU. Is there something I'm missing? Is there an example I can follow?
thanks
Michele

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Kiran Kintali
Kiran Kintali 2024-8-8，14:07
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-hardware-software-codesign-workflow-for-zynq-ultrascale-mpsoc-devices.html
You need to split the model into two subsystems or two model reference based blocks for hardware and software.
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Kiran Kintali
Kiran Kintali 2024-8-8，16:42
编辑：Kiran Kintali 2024-8-24，2:47
https://www.mathworks.com/help/simulink/examples.html?category=multicore-processor-targets&s_tid=CRUX_topnav
IP core workflow in HDL Coder generates SW interface subsystem as the subsystem to talk to the FPGA side.
This SW interface subsystem can be placed into your SW model to use Embedded Coder to build multi-core application.
There are different ways for Embedded Coder to build multi-core:
TuttoAlDoc
TuttoAlDoc 2024-8-23，13:51
Thank you very much for your answer, I will have a look

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