HDL Coder FPGA resources report

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Abel 2024-8-14，13:49

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https://ww2.mathworks.cn/matlabcentral/answers/2145294-hdl-coder-fpga-resources-report

评论： Abel about 22 hours 前

Hello,

In the HDL Coder workflow, is any way to size the FPGA requirements? In a way to be able to precisly select the FPGA that will be able to run the model simulation. Or may be a way to try seveal FPGA chips that will report utilization, without physically having the device?

We dont have neither Matlab and obviously HDL Coder, but we are considering it and after a lot of research, given that we can generate the code and even program the FPGA from Matlab, we just wonder how can we select the right FPGA chip... we are considering usning Xilinx/AMD chips... we have also considered the speedgoat options and other alternatives like NI Veristand, but that is overkill for what we are looking,... our model can be simplified to 1 DI, 2 AO and 1 AI...

And another question, the above idea, does it work only for Simulink models or it can work also for Simscape Electrical models?

Thanks

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Answer 1

Sahas 2024-8-22，11:10

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Hi @Abel,

As per my understanding you would like to get the details on FPGA’s utilization and the overview of utilization of digital circuit components without using the FPGA.

MathWorks provide this functionality using the HDL Coder Toolbox. Refer to the following steps to get HDL analysis reports of your Simulink model:

Let’s take a Simulink module compatible with HDL Coder. Run the following command in MATLAB's Command Window and open “hdlcoder_led_blinking.slx”.

>> openExample('hdlcoder/GettingStartedWithTargetingXilinxZynqPlatformExample')

Right-click on the “led_counter” block, go to HDL Code > HDL Workflow Advisor. Refer to this MathWorks documentation for more information on HDL Workflow Advisor: https://www.mathworks.com/help/hdlcoder/ug/using-the-hdl-workflow-advisor-window.html
The following image shows the configuration setup for a generic FPGA/ASIC. You can select the synthesis tool and family of FPGAs and explore more with different combinations that fit the need.

In the left pane, right-click on “Generate RTL Code and Testbench” option and select “Run to Selected Task”.

This will open a “Code Generation Report” where you can see a “High-level Resource Report” section, giving the summary of various digital circuit components used. For further information on reports generation, refer to the following link: https://www.mathworks.com/help/hdlcoder/ug/creating-and-using-code-generation-reports.html

For more accurate result analysis for a specific synthesis platform or a family of processing systems, install a synthesis tool such as Xilinx Vivado and refer to the following steps:

Run the following command to connect Vivado to MATLAB:

>> hsetupvivadoenv

Select the following configuration options. I have assumed Xilinx Vivado as the synthesis tool with the Zynq family of processing system.

Set Target Frequency to the model’s requirement, I have assumed it to be 300 MHz.
Follow the steps mentioned before and run till ‘Run Synthesis”.
This will offer a more detailed and precise utilization report that you can reference to compare the FPGA's maximum limits with its current usage.

For more information on FPGA Synthesis from Simulink, refer the following MathWorks documentation link: https://www.mathworks.com/help/hdlcoder/gs/fpga-synthesis-and-analysis-using-the-hdl-workflow-advisor.html

Simscape Electrical is compatible with HDL code generation and deployment on FPGAs. For more information on its workflows, refer to the following MathWorks documentation links:

For the MathWorks licencing needs, you can reach out MathWorks Customer Support: https://www.mathworks.com/support/contact_us.html

I hope this is beneficial. Feel free to reach out in case of any additional questions.

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Abel about 22 hours 前

Hello Sahas,

Thanks a lot for the detailed response, very helpful information on the provided links... been able to size the FPGA and been able to use Simscape to go from model to FPGA implementation will make our lifes very easy. :)

Best Regards.

Abel

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Answer 2

Pratyush 2024-8-22，6:38

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Hi Abel,

To estimate FPGA requirements for HDL Coder without physical hardware, you can:

Use HDL Coder Reports: These provide resource utilization estimates for your design.
Utilize Vendor Tools: Xilinx Vivado can simulate and estimate resource usage.
Simulate in MATLAB/Simulink: Verify functionality and refine designs before deployment.
Incorporate Simscape Electrical: While HDL Coder primarily supports Simulink, you can integrate Simscape Electrical models within Simulink for code generation.
Explore Virtual Prototyping: Use FPGA emulation tools for virtual testing and resource insights.

These methods help in selecting the appropriate FPGA, particularly for Xilinx/AMD chips, without needing the physical device.