To clarify, it looks like you are trying to run the HDL Coder generated HDL code using 40MHz clock, and the NI FPGA compilation reports that the logic cannot meet 40MHz requrement (25ns).
The recommentation is to use the HDL Coder features to find out the critical path in your design, and then use HDL Coder optimization features to insert pipeline registers to reduce the critical path to be less than 25ns.
You can use several HDL Coder features mentioned in this page:
- Critial path estimation, see section "Strategy 2: Estimate Critical Path Without Running Synthesis". This is the fastest way to get critical path, without need to run synthesis tool. You can use this feature to get quick estimate and iteratively improve your design.
- Generic ASIC/FPGA workflow, see section "Strategy 3: Annotate Critical Path By Using Backannotation". You can get more accurate timing result by running sythesis tool. You can continue improve your design until you can meet timing in this workflow
After you identified the critical path in your design, there are several recommendations for improve the design in "Step 3: Resolve Timing Failures" section.
Thanks,
Wang
