Characterisation error in HDL code generation?

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Dylan Jackway
Dylan Jackway 2024-10-6
评论： Steven Hatcher 2024-10-7
When generating RTL code for VHDL for an Artix-7 using FPGA-In-The-Loop, I'm met with these error messages and only the first section of the design is characterised. The critical path is given as 0ns.
'Error using hdlcoder.pirctx/buildCharacterizationData
Unexpected error during HDL Code Generation.
Contact support@mathworks.com with reproduction steps.
Assertion failed with debug message:
B:\matlab\src\cgir_hdl\target_analysis\ParameterizedDatabaseReader.cpp:101:paramChar
Error in characterization.readCharacterizationData
Error in slhdlcoder.HDLCoder/runPIRTransformAndCodegen
Error in slhdlcoder.HDLCoder/makehdl
Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench
Error in runGenerateRTLCodeAndTestbench
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor'
  1 个评论
Steven Hatcher
Steven Hatcher 2024-10-7
Hi Dylan,
  1. What release are you using?
  2. Are you specifying a custom timing database you generated using genhdltdb with TimingDatabaseDirectory?
Steven

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回答（1 个）

Kiran Kintali
Kiran Kintali 2024-10-7
编辑：Kiran Kintali 2024-10-7
This is an unexpected error. What version of MATLAB are you using?
Can you share the model? Do not hesitate to reach out to tech support for a workaround. Thanks

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