hW.deploy stuck after programming the bitstream

9 次查看（过去 30 天）
KH
KH 2024-12-19
评论： KH 2024-12-23，2:33
Hi,
After successfully compiling the hardware,
### Allocating external memory buffers:
offset_name offset_address allocated_space
_______________________ ______________ ________________
"InputDataOffset" "0x00000000" "23.0 MB"
"OutputResultOffset" "0x016f8000" "120.0 kB"
"SchedulerDataOffset" "0x01716000" "4.1 MB"
"SystemBufferOffset" "0x01b24000" "6.1 MB"
"InstructionDataOffset" "0x02149000" "2.4 MB"
"ConvWeightDataOffset" "0x023ad000" "49.5 MB"
"FCWeightDataOffset" "0x05525000" "2.0 MB"
"EndOffset" "0x0571a000" "Total: 87.1 MB"
### Network compilation complete.
When I try to deploy the deep learning network on my fpga, after successfully
>> hW.deploy
### Programming FPGA Bitstream using JTAG...
### Programming the FPGA bitstream has been completed successfully.
The command window recieves no feedback within about an hour. It's this step fails? But there is no error promotes,
should I stop this step manually? It's there something wrong with my program?
  2 个评论
KH
KH 2024-12-19
If the process is paused, it stays at the function ismember.m .
KH
KH 2024-12-20
Today, I wonder if it requires more time. I retry to deploy the network. However, it has been about 6 hours since the fpga bitstream is successfully loaded, the command window still has no response, even the error response.

请先登录，再进行评论。

请先登录，再回答此问题。

回答（1 个）

Sahas
Sahas 2024-12-20
Hi @KH,
This issue mostly comes when using custom boards and custom bitstreams. In my understanding, the next processes which are to load Weights of the Neural Network to the Conv and FC processors is stalling.
The following reasons might be causing this issue:
  • The weight files are incorrectly formatted or corrupted as such files can cause the loading process to hang.
  • FPGA has sufficient resources to handle the deployed network. The allocation summary you provided shows a total memory usage of 87.1 MB. Ensure that your FPGA can accommodate this.
  • The data transfer mechanism being used to load weights, DMA, is not functioning correctly.
  • The link between your host machine and the FPGA is stable. This includes checking connections and the JTAG interface.
With the abovementioned reasons, check out the log files generated in the Workspace folders for any hints.
I hope this helps!
  1 个评论
KH
KH 2024-12-23，2:33
Thanks for your comments, I have another question, is there must be a processor system or microblaze? Can the ip core directly controled by the axi manager?

请先登录，再进行评论。

类别

在 Help Center 和 File Exchange 中查找有关 Time Series and Sequence Data Networks 的更多信息

标签

产品


版本

R2024b

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by