Specify clock pins in HDL Reference Design

2025 1 28
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更新时间：2025 1 30
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I was reading over how to register a custom reference design: https://www.mathworks.com/help/hdlcoder/ug/register-a-custom-reference-design.html but the addClockInterface method doesn't appear to allow you specify what pins the actual clock is on. I was wondering where I can specify this. Would I do this inside the hdlcoder.Board definition with the addExternalIOInterface() method? If so, how do I specify a differential clock? I had also tried generating a board definition using the FPGA Board Editor which output an XML file. Is there a way to incorporate this information within the reference design definition? Thanks for any help.

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Hi John,
The addClockInterface API in HDL Coder requires you to specify a connection point in your design. For instance, if you're using Intel tools, you'll need to designate a connection point within your Qsys project for the clock input. HDL Coder will then insert the generated Qsys IP core and connect the clock port to that connection point. Here's an example of how you might use the addClockInterface method:
hRD.addClockInterface( ...
'ClockConnection', 'iopll_0.outclk1', ...
'ResetConnection', 'clk_50M.clk_reset', ...
'DefaultFrequencyMHz', 50,...
'MinFrequencyMHz', 5,...
'MaxFrequencyMHz', 500,...
'ClockModuleInstance', 'iopll_0',...
'ClockNumber', 1);
Most of our examples utilize a PLL as the clock connection point, but you can opt for other options like a Clock Bridge IP, Clock Source IP, or the differential clock you mentioned. You just need to reference it as a connection when you create your reference design.
For example, the following Intel document illustrates using a Clock Bridge IP to bring an external clock into the Qsys design: Build a System with a Top-Down Approach. In this scenario, the "ClockConnection" in the addClockInterface API can use "ext_clk/out_clk" from the Clock Bridge IP.
You can adapt this approach to fit your specific use case and the synthesis tool or board you are using.
Please let me know if this helps or if you need further clarification!
Angela

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John
John 2025-1-29
Ok, but after I create the clock in Platform Designer, I normally would go into pin planner and specify the Pin location of where the clock is coming into the FPGA. Even with a clock bridge, the external clock location needs to be specified. I don't understand how the pin mapping is done in MATLAB.
When you create a custom reference design, in addition to the files for registration, you need to create a Qsys project file that contains an Altera® Qsys embedded system design with the connections for your IP core. When you create this project, you can follow the same workflow you described to specify the pin locations of where the clock is coming from and specify that connection as the IP core clock for the project used in your reference design plugin. You can refer to this documentation page for an example: Reference Design creation using Intel Quartus Prime
John
John 2025-1-30
Would I follow this same workflow if I was using an FPGA without a hard processor? Could I use the hdlcoder.ReferenceDesign.CustomConstraints property to import the clock pin assignment?
Yes, you would still create the project and use it in the reference design plugin. In addition, you would use the CustomConstraints property of the reference design to specify the pin assignments for the clock.
For an example of a reference design plugin (and additional files) for a board without a hard processor, you can refer to our shipping reference design for the "Arrow DECA MAX 10 FPGA evaluation kit."
If you are using MATLAB R2024b, the reference design files for this board should be located in your matlabroot directory under:
toolbox\hdlcoder\boards\intel\+ArrowDECA\+qsys_base_160
For this particular board, we used hRD.CustomConstraints to add 'system_setup.tcl', which contains the pin assignments for the clock and reset connections, as shown in the snippet below:
# clock and reset
set_location_assignment PIN_M8 -to clk_clk
...
set_location_assignment PIN_H22 -to reset_reset_n
This reference design is used in the following example, in case you would like to try the complete workflow to open up an example project (note that the example does not cover the reference design creation):
Use IP Core Generation to Access DUT Registers on Pure Intel FPGA Devices

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