Hi John,
The addClockInterface API in HDL Coder requires you to specify a connection point in your design. For instance, if you're using Intel tools, you'll need to designate a connection point within your Qsys project for the clock input. HDL Coder will then insert the generated Qsys IP core and connect the clock port to that connection point. Here's an example of how you might use the addClockInterface method:
hRD.addClockInterface( ...
'ClockConnection', 'iopll_0.outclk1', ...
'ResetConnection', 'clk_50M.clk_reset', ...
'DefaultFrequencyMHz', 50,...
'MinFrequencyMHz', 5,...
'MaxFrequencyMHz', 500,...
'ClockModuleInstance', 'iopll_0',...
'ClockNumber', 1);
Most of our examples utilize a PLL as the clock connection point, but you can opt for other options like a Clock Bridge IP, Clock Source IP, or the differential clock you mentioned. You just need to reference it as a connection when you create your reference design.
For example, the following Intel document illustrates using a Clock Bridge IP to bring an external clock into the Qsys design: Build a System with a Top-Down Approach. In this scenario, the "ClockConnection" in the addClockInterface API can use "ext_clk/out_clk" from the Clock Bridge IP.
You can adapt this approach to fit your specific use case and the synthesis tool or board you are using.
Please let me know if this helps or if you need further clarification!
Angela
