Clarification on Simulink Sample Rate vs HDL Coder Target Frequency

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Jina
Jina 2025-4-4
评论： Jina 2025-4-7
Hello,
I have a question regarding the relationship between Simulink sample rate and HDL Coder target frequency.
Is it okay if the Simulink sample rate is equal to the target frequency specified in HDL Coder?
I’ve often heard that the hardware clock rate (target frequency) should generally be at least 2× the sample rate to ensure proper timing and pipelining. But in Simulink and HDL Coder, I’m unsure how strict this rule is.
Specifically:
  • If I set my Simulink sample rate to 120 MSPS and also specify 120 MHz as the HDL Coder target frequency, is this configuration valid?
  • Or should the target frequency always be greater than the sample rate, even in fully pipelined or parallel architectures?
I’d really appreciate any clarification on how these two values interact and whether matching them could lead to timing issues during synthesis or implementation.
Thanks in advance!

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Sahas
Sahas 2025-4-7
Hi @Jina,
The Simulink sample rate does not need to translate directly to the HDL Coder target frequency. The blocks can run at a Simulink rate of 1, but the user can synthesize the blocks in Vivado to whatever frequency they want, independent of this setting. We have typically found designs running upwards of 300 MHz in Xilinx devices. Depending on the speed grade of his Virtex device, the user may be able to go faster.
The clock configuration mentioned above is valid as they work independent of each other.
I hope this is beneficial!
  1 个评论
Jina
Jina 2025-4-7
Thank you for your previous explanation. I have a few follow-up questions for clarification:
  1. Does this imply that it is acceptable for the sample rate to be higher than the FPGA frequency set in Vivado? Typically, isn’t it expected that the clock rate should be higher than the sample rate?
  2. Also, when you refer to the “HDL Coder target frequency,” is that equivalent to the required AXI4-Stream Clock as configured in the RFDC settings in Vivado?
  3. I’m also a bit unclear about what you mean by saying the sample rate and target frequency are “independent” of each other. Isn’t the output sampled according to the configured clock rate?
I would greatly appreciate further details to help me fully understand these relationships.
Thank you very much for your assistance!
Sincerely, Jina

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