HDL multi rate simulation

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John
John 2026-1-20，14:40
编辑： Kiran Kintali 2026-1-20，20:26
I'm having trouble understanding how to speed up the simulation when everything is running at the hardware rate. I have a clock interface that is running at 50 MHz and I have simulink sampling rates set to 20e-9 s and then I have enabled the setting "Treat Simulink rates as actual hardware rates" in order to model to communication interface such as the AXI4 master correctly. However, the simulation comes to crawl even though controller and plant can be run at a slower rate. Is there a way I can speed up the simulation while maintaining cycle accurate fidelity?

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Kiran Kintali
Kiran Kintali about 2 hours 前
编辑：Kiran Kintali about 2 hours 前
Can you share a sample model?
It sounds like you have parts of the design that do not need to be updated at 20e-9s, if that is the case, variable step discrete solver should help with the simulation time if you are trying to speeding up the Simulink simulation of the model intended for HDL code generation.
However, there are some aspects of HDL test bench generation that would not work with this. Please reach out to tech support for additional help.

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