Can the HDL coder simulate with existing verilog/VHDL codes?

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Bo Zhang 2016-3-22

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编辑： Bo Zhang 2016-3-28

HDL coder is very convenient for hardware code generation. But now I want to reuse my previous Verilog/VHDL codes, is it possible to do that in HDL coder? Can I do co-simulation? For example, now I have the HDL code for displaying images on the LCD screen, now I want to reuse that code for displaying after the processing blocks in HDL coder.

Thanks!

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Bo Zhang 2016-3-24

Got it. http://www.mathworks.com/help/hdlcoder/external-component-interfaces.html

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Answer 1

Tim McBrayer 2016-3-22

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Yes, this is possible and easily implemented. If you want to bring existing HDL code into a HDL Coder subsystem, you can do so by using a Subsystem block and setting its HDL Architecture to "BlackBox". (Right click on the Subsystem>HDL Code>HDL Block Properties, choose the BlackBox architecture.)

Once this is done you can configure the control signals that are necessary by using the HDL Block properties dialog. The data input and output ports will be whatever the Subsystem block's interface is; you will need to match the interface of your existing code in Simulink.

For HDL code generation, you don't need anything inside the BlackBox Subsystem. HDL Coder treats it as a black box and expects the associated HDL code to exist separately. If you want to be able to simulate the full design in Simulink or use HDL Coder's testbench or cosimulation capabilities, you will need to provide a matching Simulink behavior inside the black box subsystem.

Another approach from the Simulink simulation perspective is to place your HDL code into your Simulink model with a HDL Verifier cosimulation block inside the BlackBox subsystem. This will let you test your existing code in place via cosimulation, together with the rest of the Simulink model that you are generating code for. This avoids needing to build a parallel subsystem for your existing code.

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Tim McBrayer 2016-3-25

The top subsystem is restricted to the 'module' implementation. To import HDL code with a black box, the imported code must exist underneath a top level of code that is generated by HDL Coder.

Bo Zhang 2016-3-28

编辑：Bo Zhang 2016-3-28

According to your suggestion, it works right now. Then how can I assign the physical IO pins to the simulink so that I can control the IO during simulation？Now I can do that using turnkey mode, but is it possible to do pin assignment during the FPGA-in-the-loop?

Best regards from Tony~

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