Generating VHDL
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Hi! When I try to generate a VHDL from a Simulink model I get this error *Found an unsupported unbounded loop structure. This loop may be user written or automatically generated due to the use of specific vector expressions or functions. For more information on unsupported loop structures, please refer to the documentation* which says it`s reported by Stateflow. It appears when I try to use the Fixed-Point 'min(array)' function into a Matlab Function Block to get the index of an array. 'array'type is fixed point, but the index returned by the function is 'double'. Since the VHDL generation doesn't support double data types, I think it could be the problem. But I can't fix it. Could anyone please tell me what I'm doing wrong? THANKS
回答(1 个)
Carlos
2012-3-5
1 个评论
Kiran Kintali
2012-3-24
Hi Carlos,
If you can send me the example input for 'u', I can see what is going on with the compilation issue.
Also please check out the new MATLAB to HDL workflow in HDL Coder.
http://www.mathworks.com/products/hdl-coder/?s_cid=HP_FP_SL_simhdl
Thank you.
-Kiran
kiran.kintali@mathworks.com
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