Ragarding the custom IP core generation using xilinx system generator
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Hi there,
I have designed an up counter (counts from 0 to 10) using the system generator design flow. I exported the design as IP catalog and integrated the processor with the core and developed a software application to display the counter values.
But when i display the count values, the outputs are random values from 0 to 10. I am not able to figure out what's going wrong? Can anyone please help on this?
Thanks in advance..
(i have attached images below for better understanding)
regards shashi
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/160614/image.png)
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/160615/image.png)
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/160617/image.png)
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