Axi stream interface in Xilinx system generator
显示 更早的评论
Hello there, I am trying to implement the AXI stream interface to an image negative operation in system generator. I want to verify whether my design is correct to export as an IP, in terms of enabling the bus signals. (in simulation its working fine) thanks in advance.
回答（0 个）
类别
在 帮助中心 和 File Exchange 中查找有关 C Code Generation 的更多信息
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!
Translated by 
