Why am I getting inconsistent data from my HDL Coder implementation?
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I developed an OFDM modulator using Matlab then I converted it into VHDL using HDL Coder tool. The problem is that HDL Coder generate a lot of synthesis warnings. I think that may be the problem.
Does anyone have any suggestions or had had the same problem?
I am using Matlab 2016b and ISE Design Suite 14.7 (The .vhd files generated by HDL Coder are sythesized in ISE)
回答(1 个)
Kiran Kintali
2021-5-16
0 个投票
Please reach out to support@mathworks.com with reproduction steps.
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