HDL coder simulation for video processing takes very long time. Is there way to do it faster ?

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Mohammed Shameem Hussain 2017-5-25

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评论： Mohammed Shameem Hussain 2017-5-30

采纳的回答： Bharath Venkataraman

I have discrete-time settings with fixed step of 1. The frame size of video input 480 x 640.

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Answer 1

Bharath Venkataraman 2017-5-26

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This is because of the pixel level processing. 480x640 translates to over 300K pixels per frame (not including blanking). Are you using Vision HDL Toolbox for this simulation with Frame To Pixels and Pixels To Frame blocks? If so, you have two options: 1. In Simulink, make sure that the model is in Accelerator/Rapid Accelerator mode. 2. Use a smaller image (say 60x80) to prove out your algorithm and run it on the larger frame size when you get to FPGA-in-the-Loop.

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Mohammed Shameem Hussain 2017-5-30

Thank you for your reply, yes that rapid mode works but it fails if I tried to implement the complex algorithm.

Error: Rapid Accelerator fails

IC:/PROGRA~1/MATLAB/R2017a\rtw\c\raccel -IC:/PROGRA~1/MATLAB/R2017a\rtw\c\src\rapid -w -noregistrylookup -nodeclspec TwoDimHaarWaveletTrans_1level_capi.c cpp: twodimhaarwavelettrans_1level_capi.c:41 compiler limit: line too long (more than 20253 chars)

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