Assertion failed: b:\matlab\​src\cgir_h​dl\pir_tra​nsforms\da​tarateanal​yzer.cpp:5​82:PirUtil​s::floatEq​ual(data.g​etRate(), outputSig->getRate())

2017 7 16
2 个回答
回答已采纳
更新时间：2017 7 19
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0 个投票

I am trying to convert my HDL coder project to verilog files via HDL coder workflow.
This error HDL code generation report.
Error Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())
Failed Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())
Assertion failed:
b:\matlab\src\cgir_hdl\pir_transforms\datarateanalyzer.cpp:582:PirUtils::floatEqual(data.getRate(), outputSig->getRate())
Error in slhdlcoder.HDLCoder/makehdl
Error in downstream.DownstreamIntegrationDriver/runGenerateRTLCodeAndTestbench
Error in runGenerateRTLCodeAndTestbench
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck
Error in ModelAdvisor.Node/runTaskAdvisor
Error in ModelAdvisor.Node/runToFail
Error in ModelAdvisor.Node.runtofailure
Failed Generated HDL code.
Please suggest me how to proceed. I am using Matlab 2017a.

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Walter Roberson
Walter Roberson 2017-7-16
This seems to be indicating that the data rate has been detected as being different from the output signal rate.
Isn't Matlab should be able to handle data rate automatically, because I only have the freedom to enter the main clock frequency. Please correct me if I am wrong.

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 采纳的回答

Kiran Kintali
Kiran Kintali 2017-7-19

1 个投票

Hi, we have analyzed this issue and it looks like some of your blocks are configured with different rate inputs as you can see in the picture. This is not supported by HDLCoder.
We are investigating why you were seeing the cryptic error instead of valid error message pointing you to the incorrectly configured product block. We will fix this buggy behavior in our 17b release.
For now, can you make sure the rates are consistent in your model?
we are working with Simulink team to report this error as soon as possible (ctrl-D) during rate propagation and also update HDLCoder conformance checker to report a valid message pointing to the offending block instead of the cryptic internal error.
Hope this helps.
Thanks

更多回答（1 个）

Kiran Kintali
Kiran Kintali 2017-7-17

1 个投票

can you please send me reproduction steps with a model? my team will provide a workaround for 17a. thanks.
kiran.kintali@mathworks.com

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