SIMULINK HDL coder error

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Yu Chen 2018-1-29

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编辑： Yu Chen 2018-1-29

I want to change .m to verilog code. But he will not let me turn, showing "Ports with double or single data type are not supported in the" FPGA Turnkey "workflow. Please update the data type on inport," Y ". ' what can I do?I need this in put.

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Answer 1

Kiran Kintali 2018-1-29

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编辑：Kiran Kintali 2018-1-29

Hi Yu,

You need to break the code into a testbench M file (script) and design M file (function); the testbench calls the design which is a function with inputs and outputs. Typically you will translate the design M file to Verilog code using MATLAB HDLCoder workflow after fixed-point conversion.

Please follow instructions below.

https://www.mathworks.com/help/hdlcoder/examples/getting-started-with-matlab-to-hdl-workflow.html https://blogs.mathworks.com/loren/2013/04/11/matlab-to-fpga-using-hdl-codertm/

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Yu Chen 2018-1-29

编辑：Yu Chen 2018-1-29

run.m

Thank you very much for your reply, I missed the transmission of the testbench. My input is 4 images, so it said 'HDL Code generation does not support 2D-matrices as function inputs.' And I am using norm, it said it does not support, how should I make this change?

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