HDL Coder generates parameterized VHDL/Verilog code in the following scenarios:
(1) Use of Model Arguments.
You can use model references and model arguments to generate generic parameters in the generated HDL code for Gain and Constant blocks. The model argument values should resolve to numeric data types at runtime.
(2) Use of Masked Subsystems.
You can generate reusable HDL code for subsystems that have the same tunable mask parameters, but with different values, by enabling 'MaskParameterAsGeneric':
(3) Use of Blackbox Generics.
If you are integrating legacy code using black box subsystem functionality, you can instantiate generic parameters in the module instance using the 'GenericList' parameter:
(4) Use of Address and Data width generics in RAM modules
RAMs are implemented using generic values for address and data widths.
See the attached PDF for an overview.
