Blackbox Interface : Task "Build FPGA Bitstream" unsuccessful

Question

Jean-Pierre Folcher 2018-5-7

0
链接

此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/399555-blackbox-interface-task-build-fpga-bitstream-unsuccessful

编辑： Stefanie Schwarz 2022-2-23

I would like to use Blackbox Interface with matlab R2017b. I begin with a simple vhdl code of a multiplexer with two inputs. The file Mux_JP.vhd is located in the working directory. I try to follow the documentation https://fr.mathworks.com/help/hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html

The steps 1.1 until 4.2 in the workflow advisor are successful. I have some errors in task 4.3

ERROR: [Synth 8-2948] no architecture 'rtl' for entity 'mux_jp' [c:/Users/folcher/Documents/MATLAB/BlackBox/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/ipshared/2fe2/hdl/vhdl/led_count_ip_src_led_counter.vhd:100] ERROR: [Synth 8-285] failed synthesizing module 'led_count_ip_src_led_counter' [c:/Users/folcher/Documents/MATLAB/BlackBox/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/ipshared/2fe2/hdl/vhdl/led_count_ip_src_led_counter.vhd:61] ERROR: [Synth 8-285] failed synthesizing module 'led_count_ip_dut' [c:/Users/folcher/Documents/MATLAB/BlackBox/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/ipshared/2fe2/hdl/vhdl/led_count_ip_dut.vhd:38] ERROR: [Synth 8-285] failed synthesizing module 'led_count_ip' [c:/Users/folcher/Documents/MATLAB/BlackBox/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/ipshared/2fe2/hdl/vhdl/led_count_ip.vhd:57] ERROR: [Synth 8-285] failed synthesizing module 'system_top_led_count_ip_0_0' [c:/Users/folcher/Documents/MATLAB/BlackBox/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/ip/system_top_led_count_ip_0_0/synth/system_top_led_count_ip_0_0.vhd:84] ERROR: [Synth 8-285] failed synthesizing module 'system_top' [C:/Users/folcher/Documents/MATLAB/BlackBox/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/hdl/system_top.vhd:611] ERROR: [Synth 8-285] failed synthesizing module 'system_top_wrapper' [C:/Users/folcher/Documents/MATLAB/BlackBox/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/system_top/hdl/system_top_wrapper.vhd:42]

Do you have an idea of the mistake I made ?

Thanks,

Jean-Pierre

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Gaurav Ahuja 2018-7-11

Hi. I hope this issue is resolved. This appears to be an issue in synthesis. So I feel this should be an issue in the 4.2 and should not be able to perform the task 4.3.

If the issue is still not resolved, could you provide more information?

-screenshot of the error -and the workflow that you followed.

In case if the issue is resolved, it would be nice to know the solution.

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Answer 1

Stefanie Schwarz 2022-2-23

1
链接

此回答的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/399555-blackbox-interface-task-build-fpga-bitstream-unsuccessful#answer_902955

编辑：Stefanie Schwarz 2022-2-23

To avoid this error message, try to specify the external source code as "Additional source files" in HDL Workflow Advisor. When generating HDL from a Simulink model, you can find this option in step 4.1. Create Project (when using the "General ASIC/FPGA" workflow) or step 3.2. Generate RTL Code and IP Core (when using "IP Core Generation" workflow).

See also: https://www.mathworks.com/help/releases/R2021b/hdlcoder/ug/hdl-workflow-advisor-tasks.html