Using unit delay with HDL Code Generator

1 次查看（过去 30 天）
Maria
Maria 2018-10-25
Hello! I'm trying generate HDL code for next block, which calculates derivative of input signal with Sample Time = 200 us.
How I can provide it for FPGA with clock 100 MHz (clock period 10 ns)? I must delay signal in "Delay" block for one sample time = 200 us, but I have delay for one period of clock = 10 ns.

请先登录，再回答此问题。

回答（0 个）

类别

在 Help Center 和 File Exchange 中查找有关 HDL Coder 的更多信息

标签

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by