These page describes how to generate code with synchronous or asynchronous reset.
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Asynchronous
Use asynchronous reset logic. This reset logic samples the reset independent of the clock signal.
The following process block, generated by a Unit Delay block, illustrates the use of asynchronous resets. When the reset signal is asserted, the process block performs a reset, without checking for a clock event.
Unit_Delay1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Unit_Delay1_out1 <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
Unit_Delay1_out1 <= signed(x_in);
END IF;
END IF;
END PROCESS Unit_Delay1_process;
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