>> help importhdl
if you have Synthesizable subset of verilog you can import into Simulink using "importhdl" functionality. We do not yet support VHDL. if you can please share your sample design with us kiran.kintali@mathworks.com
You can also bring vhdl/verilog using blackbox capability and integrate legacy IP with generated HDL code.
You can also import vhdl/verilog as a cosimulation block and use HDL Verifier product to simulate with a supported HDL Simulator.
Please check further on these topics in product documentation.
