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Why can I not change the architecture of my subsystem to Black Box?

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dr446
dr446 2019-2-12
评论： Sina Aghli 2020-1-18
I am using R2018b. My end goal is to use FPGA in the Loop programming. I have verilog files that I want to include as a black box but I cannot change the architecture of my simulink subsystem to a blackbox.

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回答（3 个）

Raghav Singhal
Raghav Singhal 2019-2-20
Please see this documentation page for details on generating a black box interface:
https://www.mathworks.com/help/hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html
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dr446
dr446 2019-2-26
Thanks but I have already read it. For some reason, the subsystem is stuck at a module and cannot be changed to a black box.

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Antti Mattila
Antti Mattila 2019-12-30
I seem to have the same problem. The "BlackBox" architecture option is not available for a subsystem. (I'm using 2018b also).
For some subsystem/refrenced models it is. This seems arbitrary.
Sina Aghli
Sina Aghli 2020-1-18
I'm having the same issue(R2019a), has this feature been deprecated?
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Sina Aghli
Sina Aghli 2020-1-18
I create a HDL/Subsystem and then rightckick then HDL Code -> HDL Block Properties ...
then in "HDL properties::Subsystem" window under Implementation->Architecture, the only available option is "Module" and there is no blackbox option

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