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Error in conversion of simulink model into verilog code?

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SUKUMAR NAGINENI 2019-3-17

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回答： Kiran Kintali 2019-3-17

采纳的回答： Kiran Kintali

Hello,

We are getting an error while conversion of Simulink model into Verilog code using HDL coder. Anyone can resolve this problem.

The details of the current MATLAB version and the error attached below.

MATLAB 2015 b (32-bit).

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Kiran Kintali 2019-3-17

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Absence of the necessary files shows you seem to have installation issues.

Can you please do a clean reinstall and if it doesn't help can you contact MathWorks install team support?

Thanks

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