IP Core generation for Generic Xilinx Platform without any AXI interface

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nagendra badiger
nagendra badiger 2019-5-3
回答： Morris 2020-11-19
Hello ,
I'm trying to implement a design on Custom board with ATrix-7 series Fpga. I want to generate an IP core which doesn't have any AXI-master/slave or AXI-4 lite interface. Even though I map all the input and output ports to external ports, still the generated IP core contains Enable and reset ports mapped to AXI accessible registers. I tried to custom code it but had no success. Please any one let me know, How I can remove these default AXI_ports (kindly refer the attached picture 1). I this link https://de.mathworks.com/help/hdlcoder/ug/generate-a-custom-ip-core.html, Mathwork reports that one can generate IP core without AXI4 slave interfaces, by clearing the checkbox in the HDL work flow advisor. I'm using Matlab2018_b, I followed all the mentioned steps, but on the last step I dont see an option to uncelar the check box(PS:Fig 2).
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Morris
Morris 2020-11-18
Hey,
I have the same problem. Tried it with 2019a, 2019b and finally now also with 2020b. My issue is that when I begin with a fresh start of the HDL workflow advisor, I CAN uncheck the AXI4 slave interface. However, when I generate the code and Vivado project, the AXI interface option is automatically checked again. The same happens when I set the option via the HDL block properties. I can turn the interface off, but after code generation it is set back to 'on'. The actual interface obviously is in fact being implemented, e.g. when I look at the Vivado block diagram of the generated project.
Any ideas? Help is greatly appreciated.

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采纳的回答

nagendra badiger
nagendra badiger 2019-5-3
Found the answer, the option is available in only Matlab 2019a

更多回答（1 个）

Morris
Morris 2020-11-19
Okay, a colleague was able to help me out. I selected the Zedboard as a target in task 1.1 of the workflow advisor and this automatically activates the AXI slave interface. I am now targeting generic Xilinx devices and the above mentioned check box remains cleared, so now I get an IP core without the AXI interface. Nice!
@Staff: That was really exasperating though, you might want to add some clear notification or something.

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