FPGA in the Loop (timing constraints?)

2 次查看（过去 30 天）

显示更早的评论

legendbb 2012-8-20

0
链接

此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/46371-fpga-in-the-loop-timing-constraints

Where were timing constraints defined for FIL?

I've noticed the .ucf file generated. But where was the input to those values?

What's the proper way to change click rate if I'd rather run FIL in a different clock rate?

Thanks

2 个评论
显示无隐藏无

legendbb 2012-9-10

编辑：legendbb 2012-9-10

Read deep in one of the FIL project, found out the clock feed to DUT is actually clkin/8. For Xilinx sp605, CLKDV_DIVIDE = 8, clkin to DUT is 200MHz/8 = 25MHz.

I don't know if adjusting timing directly inside FIL project will screw up the whole synchronous or not. I will try out.

But lack of documentation nor comments here, I don't really understand what's the proper way to run DUT FIL at faster speed.

Jonathan Rodrick 2012-12-9

Hi, did you manage to figure out how to manage the clock rate? I'm using an Altera board. My DUT clock is also 25MHz and cannot figure out how to change this. I've tried constraining my designs clock to 50MHz and adding the constraint file to FIL wizard but this didn't work.

Thanks, Jon

请先登录，再进行评论。

请先登录，再回答此问题。