Is FTDI USB-JTAG supported for FPGA-in-the-Loop (FIL) simulation with HDL Verifier?
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MathWorks Support Team
2018-10-26
编辑: MathWorks Support Team
2023-11-23
I use the example model "fil_pid.slx". I go through HDL Workflow Advisor for this model to load it to my Xilinx FPGA board. All of the steps pass and the model is successfully loaded onto the board. When I try to run the model with FPGA-in-the-Loop (FIL), however, I get the following error when using MATLAB R2019a:
Did not find any Digilent(R) JTAG cable. Make sure that the cable is connected to your computer.
Failed to initialize the RTIOStream library.
My board uses an FTDI chip for its USB-JTAG connection. I have checked my JTAG connection and I am able to see that I am connected to the board. I am able to successfully load programs through this connection.
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MathWorks Support Team
2023-11-23
编辑:MathWorks Support Team
2023-11-23
UPDATE: Starting in R2021b, FTDI USB-JTAG connections are supported for FPGA-in-the-Loop (FIL) simulations.
In R2021a and earlier, only MATLAB as AXI Master and FPGA Data Capture applications are supported with an FTDI USB-JTAG connection, while FIL simulations are not. This will cause the error seen above.
See the link below for JTAG requirements with HDL Verifier (adjust the URL to match your MATLAB release):
For boards using a Digilent JTAG chip, FIL applications have been supported since R2015a. For boards with a standard Xilinx 14-pin JTAG connector, use an HS2 or HS3 cable from Digilent and use that for JTAG FIL simulations:
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