How do I add FPGA data capture IP core in existing Vivado project?

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Adriaan Sadie
Adriaan Sadie 2019-7-23
回答： Dave Gutierrez 2019-8-1
I am using the FPGA data capture component from Matlab (generateFPGADataCaptureIP) to generate a logic analyzer IP core which I can import to my existing project in Vivado (v 2018.2). The component generates a lot of files, except for a .xml file, which is apparently the one Vivado requires to recognize the IP core.
I already added the IP directory to to catalog in Vivado, but when I right click on it and try to "Add IP to repository...", I get a critical warning saying:
Warning.PNG
How can I generate the required xml file in order to include it in my project?

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回答（2 个）

Dave Gutierrez
Dave Gutierrez 2019-7-31
Adriaan,
You need to add the generated HDL files to your project.
It is not a Vivado IP.
Thanks,
David G
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Adriaan Sadie
Adriaan Sadie 2019-8-1
Hi David
I added all the hdl files as source files with no errors, but when I tried to synthesize it took more than 90 minutes and did not even finish. My project is really small at the moment, so I can't see how it can take that long. Do you think there is something that I'm missing?
Thank you
Adriaan

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Dave Gutierrez
Dave Gutierrez 2019-8-1
Hi Adriaan,
If you are targeting a large board it might take a while to generate the bitstream. If you are not getting any error and no file is being generated I would recommend contacting Xilinx or posting in their forums. They will be able to provide better assistance.
Thanks,
David G

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