Why do I receive an assertion in portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp

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Chao-Hwa Chen
Chao-Hwa Chen 2019-9-4
回答： Kiran Kintali 2019-9-5
When I try to generate HDL code for my model in R2019a, I receive an assertion error below. How do I resolve this error?
Assertion failed: b:\matlab\src\pir_core\base_core\portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp <Component CtxName="NLMS_loopback_ARM" RefNum="c204" UserName="crp_temp" RTTIClass ="class pir::NetworkInstComp" Network="n3"/>
Thanks a lot in advance.

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采纳的回答

Kiran Kintali
Kiran Kintali 2019-9-4
This is not expected and you are run into an internal error.
Can you submit reproduction steps to support@mathworks.com?
thanks
  1 个评论
Chao-Hwa Chen
Chao-Hwa Chen 2019-9-5
I tried to compile the HDL code in the HDL_TX_DUT block to the attached Simulink file with model_init.m as the initialization file. I right-click the HDL_TX_DUT block to run the HDL Workflow advisor. I pass through Steps 1, 2 and 3.1. When I run Step 3.2, the error happens.
Failed Assertion failed: b:\matlab\src\pir_core\base_core\portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp
Error using hdlcoder.pir/retimeAndBalanceCRPs
Assertion failed:
b:\matlab\src\pir_core\base_core\portmgr.cpp:340:Error: Invalid port index 13 requested when 12 is the max port index for comp <Component CtxName="NLMS_loopback_ARM" RefNum="c204" UserName="crp_temp" RTTIClass ="class pir::NetworkInstComp" Network="n3"/>
Error in slhdlcoder.HDLCoder/makehdl
Error in slhdlcoder.HDLCoder/makehdlturnkey
Error in downstream.DownstreamIntegrationDriver/runIPCoreCodeGen
Error in generateIPCore
Error in Simulink.ModelAdvisor/executeCheckCallbackFct
Error in Simulink.ModelAdvisor/run
Error in Simulink.ModelAdvisor/runCheck

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更多回答（2 个）

Chao-Hwa Chen
Chao-Hwa Chen 2019-9-5
I found the problem. It is that I put the upsampling before the HDL block and then the downsampling within the HDL block. That causes the internal error. I changed the design to remove both the upsampling/downsampling blocks at all. Now it passes Step 3.2 now.
Kiran Kintali
Kiran Kintali 2019-9-5
Thank you. Great to know you found a reasonable workaround for the issue.
If you can still share the reproduction steps for the original model it would be helpful to continue to improve the software and code generation mechanism for the original scenerio.

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