how to implement HDL coder "clock enable"

Question

Lennert Es 2019-10-8

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https://ww2.mathworks.cn/matlabcentral/answers/484243-how-to-implement-hdl-coder-clock-enable

评论： SHIYU SONG 2022-3-10

Dear all,

I am using HDL coder to generate VHDL code for an FPGA.

When I use certain blocks such as a counter ("HDL counter" or "counter limited" for example), the VHDL code also generates a "clk_enable" input on top of the normal "clk".

I have assigned the "clk" pin to the onboard 50MHz clock, but how should I assign the "clk_enable" pin?

I would like the counter to run continuously so smehow the clk_enable should remain HIGH.

Kind regards,

Lennert

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Answer 1

Priyanshu Mishra 2019-10-11

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https://ww2.mathworks.cn/matlabcentral/answers/484243-how-to-implement-hdl-coder-clock-enable#answer_395838

Hi Lennert,

To run the counter continuously, set the clk_enable signal to ‘1’. For information on clock enable signal, I would suggest you go through the following link

https://www.mathworks.com/help/hdlcoder/ug/clock-enable-settings.html?searchHighlight=clock%20enable&s_tid=doc_srchtitle#responsive_offcanvas

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SHIYU SONG 2022-3-10

Hi，

I have the same question that I need to run the counter continuously, which means the clk_enable signal should always be 1. So, how can I remove this automatically generated port?

Thank you !

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