HDL Coder to / downto order

Question

Michael Felger 2019-11-13

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https://ww2.mathworks.cn/matlabcentral/answers/490836-hdl-coder-to-downto-order

编辑： Kiran Kintali 2024-1-9

采纳的回答： Kiran Kintali

Hi,

I'm using HDL Coder to generade VHDL code for a simulink block.

In the entity, the port order is generated as follow:

for fixed-point variables, the output port is std_logic_vector(n downto 0)
for boolean vector (Simulink Port dimension: [1 n]), the output port is std_logic_vector(0 to n)

Is it possible to change the order (to / downto), that all output ports have the same direction, and are not mixed for one entity?

My goal is to have downto for all outputs.

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Answer 1

Kiran Kintali 2019-11-14

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https://ww2.mathworks.cn/matlabcentral/answers/490836-hdl-coder-to-downto-order#answer_401422

This is a limitation due to an early decision made to emit vector of boolean to use 'TO' syntax and is not currently customizable.

A potential workaround is to concatenate boolean vector to a single signal of ufixN type using BitConcat block and seperating input scalar signal inside DUT back to vector of boolean using BitSlice blocks.

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Answer 2

Kiran Kintali 2023-9-8

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https://ww2.mathworks.cn/matlabcentral/answers/490836-hdl-coder-to-downto-order#answer_1305846

编辑：Kiran Kintali 2024-1-9

The control is now available starting R2023b release for boolean arrays.

https://www.mathworks.com/help/releases/R2023b/hdlcoder/release-notes.html

Generate code for Boolean array with MSB-to-LSB convention

You can now generate code for an array of boolean data in most significant bit (MSB) to least significant bit (LSB) convention. For example, a subsystem with boolean input and output data, the generated VHDL code with the DOWNTO convention has this form:

ENTITY Subsystem IS
PORT ( In1    : IN  std_logic_vector(4 DOWNTO 0); -- boolean [5]
       Out1   : OUT std_logic_vector(4 DOWNTO 0)  -- boolean [5] );
END Subsystem;

You can use this functionality for the VHDL®, Verilog®, and System Verilog target languages.

To revert to the old behavior you can use this option.

>> makehdl(<pathtodut>, 'BooleanVectorDownTo', 'off')

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Eckhard Hennig 2024-1-9

Is there an option in R2023b that allows the indexing order to be switched back to the previous behavior (0 to ...)? Generally, I'm happy about the change to the "downto" order, but I need to restore the previous behavior for compatibility with a proprietary add-on that relies on the "to" order.

Kiran Kintali 2024-1-9