Delay balancing unsuccessful because Signal rate of value inf found.

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Re4s
Re4s 2019-12-2
评论： Kiran Kintali 2020-5-25
Hello,
I am getting this error when generating RTL Code and IP Core at the HDL Workflow Advisor :
Delay balancing unsuccessful because Signal rate of value inf found. Offending Block:QAE_V7/Decoder/.
This message only occurs when i want to multiply a signal with a constant greater than 3. For this mulitplication I used the gain block and the product block from the HDL Code Library but there is no difference.
I already checked all blocks for an explicit sample time. Without this muliplication there is no error.
  2 个评论
Bharath Venkataraman
Bharath Venkataraman 2019-12-3
Any chance you could upload some or all of the model so we can take a look at the issue?
Re4s
Re4s 2019-12-4
1.PNG
The input A is defined as a boolean signal from an encoder. In this "model" there is the problem with the multiplication with the gain block. If i want to multiply with 2 and this gain block there is no problem.
Unbenannt.PNG

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回答（5 个）

Kiran Kintali
Kiran Kintali 2020-5-23
编辑：Kiran Kintali 2020-5-23
Your model is partially converted to fixed-point. Can you check for absence of floating-point if your intent is HDL code generation from fixed-point model? If you do intend to use flaoting-point types in the model you need to enable "Native Flating Point" code generation capability which will instantiate necessary floating-point units in the generated HDL code.
After removing 4 such DTC blocks and marking the constants int16 type I was able to generate code.
### Estimated critical path for design: hdl_prj\hdlsrc\Sin\criticalPathEstimated.m
### Blocks that are not characterized for Critical Path Estimation: hdl_prj\hdlsrc\Sin\highlightCriticalPathEstimationOffendingBlocks.m
### To clear highlighting, click the following MATLAB script: hdl_prj\hdlsrc\Sin\clearhighlighting.m
### Begin VHDL Code Generation for 'Sin'.
### Working on Sin/DUT_21/AD_Sample_5MHz as hdl_prj\hdlsrc\Sin\AD_Sample_5MHz.vhd.
### Working on Sin/DUT_21/DA_Sample_2MHz as hdl_prj\hdlsrc\Sin\DA_Sample_2MHz.vhd.
### Working on Sin/DUT_21 as hdl_prj\hdlsrc\Sin\DUT_21.vhd.
### Generating package file hdl_prj\hdlsrc\Sin\DUT_21_pkg.vhd.
### Generating HTML files for code generation report at Sin_codegen_rpt.html
### Creating HDL Code Generation Check Report DUT_21_report.html
### HDL check for 'Sin' complete with 0 errors, 1 warnings, and 2 messages.
### HDL code generation complete.
Thanks
  1 个评论
rong he
rong he 2020-5-24
Thanks for your answers，but it still have the same problem when i set all of them to fixed point. The attachment is my simulation file.

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Kiran Kintali
Kiran Kintali 2019-12-3
Can you run HDL model advisor check shown below to see if you can detect the block? hdlcoder_inf_check.PNG
If the block with Inf sample time is not in the DUT then this may be a bug. please contact support@mathworks.com with reproduction steps.
Thanks
Kiran Kintali
Kiran Kintali 2019-12-4
Can you share the model and the version of MATLAB you are using that exhibits this behavior? Thanks.
rong he
rong he 2020-5-23
this is my simulation model. Thank you!
Kiran Kintali
Kiran Kintali 2020-5-24
I still see "Inf" sample times in the model.
Found the Model was feeding 'Inf' sample time into the DUT. This is not allowed for HDL code generation.
hdlmodelchecker('Sin3/DA_Settings')
Ran the check for Infite sample times in the model advisor check for HDL; Found several offending blocks; Clicked "Modfiy Settings" to automatically set the constant blocks with "Inf" sample time to -1. This will force all blocks in DUT have the same rate propgated via backward propagated (10e-9) or what ever is feeding the rest of the model.
>> makehdl(gcb)
### Generating HDL for 'Sin3/DUT_21'.
### Using the config set for model Sin3 for HDL code generation parameters.
### Starting HDL check.
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 0: 2 cycles.
### Output port 1: 2 cycles.
### Output port 2: 2 cycles.
### Output port 3: 2 cycles.
### Output port 4: 2 cycles.
### Output port 5: 2 cycles.
### Output port 6: 2 cycles.
### Output port 7: 2 cycles.
### Output port 8: 2 cycles.
### Output port 9: 2 cycles.
### Output port 10: 2 cycles.
### Output port 11: 2 cycles.
### Output port 12: 2 cycles.
### Output port 13: 2 cycles.
### Output port 14: 2 cycles.
### Output port 15: 2 cycles.
### Output port 16: 2 cycles.
### Output port 17: 2 cycles.
### Output port 18: 2 cycles.
### Output port 19: 2 cycles.
### Output port 20: 2 cycles.
### Output port 21: 2 cycles.
### Output port 22: 2 cycles.
### Output port 23: 2 cycles.
### Output port 24: 2 cycles.
### Output port 25: 2 cycles.
### Output port 26: 2 cycles.
### Output port 27: 2 cycles.
### Output port 28: 2 cycles.
### Estimated critical path for design: hdl_prj\hdlsrc\Sin3\criticalPathEstimated.m
### Blocks that are not characterized for Critical Path Estimation: hdl_prj\hdlsrc\Sin3\highlightCriticalPathEstimationOffendingBlocks.m
### To clear highlighting, click the following MATLAB script: hdl_prj\hdlsrc\Sin3\clearhighlighting.m
### Begin VHDL Code Generation for 'Sin3'.
### Working on Sin3/DUT_21/AD_Sample_5MHz as hdl_prj\hdlsrc\Sin3\AD_Sample_5MHz.vhd.
### Working on Sin3/DUT_21/DA_Sample_2MHz as hdl_prj\hdlsrc\Sin3\DA_Sample_2MHz.vhd.
### Working on Sin3/DUT_21 as hdl_prj\hdlsrc\Sin3\DUT_21.vhd.
### Generating package file hdl_prj\hdlsrc\Sin3\DUT_21_pkg.vhd.
### Generating HTML files for code generation report at Sin3_codegen_rpt.html
### Creating HDL Code Generation Check Report DUT_21_report.html
### HDL check for 'Sin3' complete with 0 errors, 2 warnings, and 2 messages.
### HDL code generation complete.
HDLCoder generated VHDL code without any errors and no delay balancing errors due to offending inf sample times.
Thanks

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