Dual clock Simulink design to implement in HDL Coder using "clock_enable" constraint

Alex Aronov

2020 2 3

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8 次查看（30 天）

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Hello,

I have dual clock Simulink design to implement in HDL Coder. Clocks are 250 and 125 MHz.

I need to setup HDL Coder as single clock input. Thus, the only way to make slow clock (125 MHz) would be by using clock_enable. HDL Coder does not pass slow clock information to Vivado, so the whole design is routed at the fast clock (250 MHz). This makes timing fail in Vivado. It would be easy to meet timing if Vivado routed at the correct clock rates (both fast and slow). How do I tell Vivado in HDL Coder to use clock_enable constraint for slow part of the design?

Thanks!