HDL Coder reset - asynchronous and synchronous possible?

2020 3 26
1 个回答
回答已采纳
更新时间：2020 3 29
11 次查看（30 天）

0 个投票

Hi,
is it possible to generate HDL code with both, asynchronous and synchronous reset?
https://de.mathworks.com/help/hdlfilter/ports-and-resets.html#bsuyrsd

请先登录，再回答此问题。

 采纳的回答

Kiran Kintali
Kiran Kintali 2020-3-29

0 个投票

Currently it is not possible. The generated code uses either sync or async reset. Can you explain your usecase?
Thanks

更多回答（0 个）

类别

在 帮助中心 和 File Exchange 中查找有关 AMD FPGA and SoC Devices 的更多信息

产品

版本

R2019b

标签

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by