Yes, this workflow is supported, and the documentation includes examples illustrating potential usages. This approach requires "targeted" code generation, in which Xilinx System Generator for DSP generates the code for Xilinx blocks, and HDL Coder™ generates code from Simulink blocks.
This overall workflow for Xilinx System Generator within HDL Coder is described at this documentation page; pay particular attention to the requirements and limitations listed near the bottom of the page.
Furthermore, the following example may be helpful when getting started. It illustrates the workflow, and elaborates on how this works: "HDL Coder™ generates HDL code from the Simulink blocks, and uses Xilinx System Generator to generate HDL code from the Xilinx System Generator Subsystem blocks."
