Can I generate HDL Code for models with Xilinx System Generator blocks?

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MathWorks Support Team
编辑:MathWorks Support Team 2020-9-25
Yes, this workflow is supported, and the documentation includes examples illustrating potential usages. This approach requires "targeted" code generation, in which Xilinx System Generator for DSP generates the code for Xilinx blocks, and HDL Coder™ generates code from Simulink blocks.
This overall workflow for Xilinx System Generator within HDL Coder is described at this documentation page; pay particular attention to the requirements and limitations listed near the bottom of the page.
Furthermore, the following example may be helpful when getting started. It illustrates the workflow, and elaborates on how this works: "HDL Coder™ generates HDL code from the Simulink blocks, and uses Xilinx System Generator to generate HDL code from the Xilinx System Generator Subsystem blocks."

更多回答(2 个)

Kiran Kintali
Kiran Kintali 2020-4-20
If you have access to R2018a can you try to reproduce the issue in that release? We suspect this is already resolved in 18a release.
Thanks.

Kiran Kintali
Kiran Kintali 2020-4-20
While running the simulation using the TCL script generated by HDL Coder, HDL Coder generates SysGen_with_HDL_Coder_CustomTCL_run.tcl script that is using a Vivado simulation command, launch_modelsim.
The TCL command “launch_modelsim” was supported in older versions of Vivado. Vivado 2017.1 supports following commands to use ModelSim simulator.
set_property target_simulator "ModelSim" [current_project]
launch_simulation -mode "post-synthesis" -type "functional"
In the example above, the options -mode “post_synthesis” and –type “functional” are just for example and should be replaced with an appropriate options.
This issue should be resolved in 18a and older releases. Please confirm.
Thanks

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