Generating HDL code error in the example "HDL Optimized QPSK Receiver with Captured Data"
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I am doing the example for "HDL Optimized QPSK Receiver with Captured Data"(https://www.mathworks.com/help/comm/examples/hdl-optimized-qpsk-receiver-with-captured-data.html)
and got a below message.
1) Generating DUT using verilog was successful. (Default language was set to VDHL)
2) Generating Test bench was failed.
How can I fix it? Could you help me?
回答（1 个）
Kiran Kintali
2020-4-12
0 个投票
This is a bug in HDL test bench generation. Please reach out to support@mathworks.com with reproduction steps.
1 个评论
Kiran Kintali
2020-4-18
What version of MATLAB you are using when you encountered this error? Thanks.
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