VHDL Coder Error: "Found an unsupported unbounded loop structure"
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Hello, I am trying to convert this code into HDL. I am getting these errors but it won't tell me the location. I have already changed all the for loops into static ones. What can I do to fix this? I'm new to matLAB and also to HDL Coder so I don't know if the way I'm going through the matrices is supported or not.
OneRVHDLtest_fixpt:0 Error Found an unsupported unbounded loop structure, at Function 'sortIdx' (#53.18405.18482), line 530, column 1 Function 'sortIdx' (#53.17932.18022), line 514, column 5 Function 'sortIdx' (#53.11676.11779), line 333, column 5 Function 'sortIdx' (#53.3899.4005), line 105, column 13 Function 'sort' (#45.3187.3277), line 72, column 5. This loop may be user written or automatically generated due to the use of specific vector expressions or functions.
OneRVHDLtest_fixpt:0 Error Found an unsupported unbounded loop structure. This loop may be user written or automatically generated due to the use of specific vector expressions or functions.
OneRVHDLtest_fixpt:0 Error Found an unsupported unbounded loop structure, at Function 'sortIdx' (#53.18405.18482), line 530, column 1 Function 'sortIdx' (#53.17756.17862), line 507, column 9 Function 'sortIdx' (#53.11676.11779), line 333, column 5 Function 'sortIdx' (#53.3899.4005), line 105, column 13 Function 'sort' (#45.3187.3277), line 72, column 5. This loop may be user written or automatically generated due to the use of specific vector expressions or functions.
OneRVHDLtest_fixpt:0 Error Found an unsupported unbounded loop structure, at Function 'sortIdx' (#53.19212.19330), line 561, column 13 Function 'sortIdx' (#53.17756.17862), line 507, column 9 Function 'sortIdx' (#53.11676.11779), line 333, column 5 Function 'sortIdx' (#53.3899.4005), line 105, column 13 Function 'sort' (#45.3187.3277), line 72, column 5. This loop may be user written or automatically generated due to the use of specific vector expressions or functions.
OneRVHDLtest_fixpt:0 Error Found an unsupported unbounded loop structure. This loop may be user written or automatically generated due to the use of specific vector expressions or functions.
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Kiran Kintali
2020-4-18
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Typically this error means you have loop bounds that are not static and determinable at compile time. Compiling MATLAB functions to synthesizable hardware targeting FPGA/ASIC designs require fixed size loops.
Please provide the testbench and MATLAB HDLCoder project for this design.
Thank you.
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