Hi, i'm trying to use HDL coder tool.
I used Matlab function block and make a simple as belowed:
function y = fcn(en,in,clk)
z= int16(zeros(9,9));
y = int16(zeros(0));
if clk ==1
if en ==1
for i=0:9
for j=0:9
z(i,j) =in;
end
end
end
y=z(1,1);
end
and when i generate to RTL code (verilog), the always loop is used en and clk singnal for the trigger
always @(clk && en) begin
.......
I expected as belowed
alsways @(posedge clk) begin
if (en) begin
......
If any have experience please help me.
Thank you and best regards.