What is the good manner of generating the HDL Code of a mixed Simscape/Simulink model ?

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Samuel Quiniou 2020-7-20

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编辑： Kiran Kintali 2020-7-20

Hello,

I have to generate the HDL Code of a mixed Simscape/Simulink model. All the model (Simscape + Simulink) must fit into one FPGA.

The Simscape part contains 6 Simscape networks with only Electrical blocks. The Simscape networks are connected by Simulink/Simscape converter blocks and Simulink blocks.
The Simulink part contains Simulink blocks that are compatible with the HDL Code generation.

I followed the tutorials of how to generate HDL Code from a Simscape model, but none of them shows the example of generating the HDL Code of a mixed Simscape/Simulink model.

In my Simscape/Simulink model, when I use the SSHDL advisor tool

It generates 6 State Space Simulink implementation submodels of the 6 Simscape networks.
The 6 State Space Simulink implementation submodels are not connected with the original Simulink blocks.
The original Simulink part is not present in the SSHDL model.

So when I use the HDL Workflow advisor tool, the HDL Code does not contain all the functionnalities of my original model.

What is the good manner of generating the HDL Code of a mixed Simscape/Simulink model ?

Thank you for your answers.

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Kiran Kintali 2020-7-20

编辑：Kiran Kintali 2020-7-20

Can you try 20b pre-release which supports Automatic replacement of Simscape subsystem with state-space implementation?

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Answer 1

Kiran Kintali 2020-7-20

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编辑：Kiran Kintali 2020-7-20

Simscape Hardware-in-the-Loop Workflow

Automatic replacement of Simscape subsystem with state-space implementation

In R2020b, the Simscape HDL Workflow Advisor automatically replaces the Simscape™ subsystem with the state-space implementation in the HDL implementation model. You do not have to modify the HDL implementation model, and can directly generate HDL code for the model and then deploy the code onto Speedgoat FPGA I/O modules.

In addition, when you select the Generate validation logic for the implementation model check box, the Advisor generates the HDL implementation model and a state-space validation model.

See Modeling Guidelines for Simscape Subsystem Replacement.

Automatic setting of number of solver iterations in Simscape HDL Workflow Advisor

Previously, when you ran the Simscape HDL Workflow Advisor, in the Generate implementation model task, the Number of solver iterations was specified as 5 for switched linear models. When you generated the HDL implementation model, in some cases, you had to iterate multiple times to get the optimal number of solver iterations.

In R2020b, depending on your Simscape model, the Advisor automatically determines an optimal number of solver iterations that causes the model simulation to converge and avoids exceeding the threshold value for real-time deployment.

See Using Number of Solver Iterations.

Mapping of state-space parameters to RAM in HDL implementation model

For large Simscape models, the generated HDL implementation model can have large state-space parameters. These state-space parameter matrices consumed a large number of FPGA lookup table resources on the FPGA, and might cause the design to not fit on the target FPGA device.

To save lookup table resources, you can now map the state-space parameter matrices to Block RAM resources on the FPGA. In the Generate implementation model task, the Map state space parameters to RAMs setting is specified as Auto, which maps state-space parameters to RAMs.

See Optimize HDL Implementation Model Generated from Simscape.