Error with cosimulation on tunable parameters

2 次查看（过去 30 天）
kimi
kimi 2020-12-1
回答： Kiran Kintali 2020-12-8
Hello all!
I'm having trouble with conducting FPGA In the Loop. I'm getting this error regarding cosimulation and tunable parameters. Do you know of a solution or a bypass? The objective is to do a FPGA in the loop simulation of a field oriented control based current controller.

请先登录，再回答此问题。

回答（2 个）

Kiran Kintali
Kiran Kintali 2020-12-2
This is a limitation in the cosimulation test bench generation.
Can you consider using stand-alone testbench with HDL Simulator?
  1 个评论
kimi
kimi 2020-12-8
Ok. Is there no way for me to integrate the Zedboard? Can I do FPGA data capture?

请先登录，再进行评论。

Kiran Kintali
Kiran Kintali 2020-12-8
https://www.mathworks.com/help/supportpkg/xilinxzynqbasedvision/ug/fpga-targeting-workflow.html
yes, You can target zed board using HDL Coder. FPGA data capture is another good way to capture signals. please contact support@mathworks.com

类别

在 Help Center 和 File Exchange 中查找有关 FPGA, ASIC, and SoC Development 的更多信息

标签

产品


版本

R2020a

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by