HDL Coder: How to create a resettable delay that triggers on rising edge

Question

Dominik Hiltbrunner 2020-12-9

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评论： Dominik Hiltbrunner 2020-12-11

Hello Community

I'm trying to implement a limited counter which has a variable upper limit, i.e. the upper limit is given by a signal.

This proposed solution does this. The problem is that this solution is not HDL code generation compatible. If I try to generate VHDL code, I get the follwing error from the resettable delay block:

Only 'Level' external reset mode on the Delay block is supported in 'Classic' mode.

If I set the External reset to "Level" mode, the behaviour is no longer correct.

What do I have to do in order to create a resettable delay block that behaves in the same way as a flip flop that resets on the rising edge?

Furthermore, what is the "Classic mode" in this error message? I cannot find an answer to this in the documentation.

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Answer 1

Kiran Kintali 2020-12-10

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https://ww2.mathworks.cn/matlabcentral/answers/688794-hdl-coder-how-to-create-a-resettable-delay-that-triggers-on-rising-edge#answer_571674

编辑：Kiran Kintali 2020-12-10

在 MATLAB Online 中打开

Please find attached two variations of the model generating HDL code.

Simulink “Counter Limited” block with dynamic upper limit

One using MATLAB function block with the following code

function y = fcn(u)
persistent count;
if isempty(count)
    count = int8(0);
end
if count > u
    count = int8(0);
end
y = count;
if count <= u
    count = count + 1;
end
end