Set up HDL verifier

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Mohamed BAGHDADI
Mohamed BAGHDADI 2021-1-16
回答： YP 2022-11-21
how can i fix this problem?
PS: I work with MATLAB 2019b, Quartus Prime 18.1 & FPGA cyclone IV GX.

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YP
YP 2022-11-21
The command line window shows "Expected programming file not generated".
You may need to check the project log see why the bit file gen failed.

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