periodic sample time error

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vikas
vikas 2013-5-14
i am simulating speed control of BLDC using FPGA .i have completed the model but i m getting one error "The periodic sample time 1000000.0 is not allowed because the ratio of this sample time over base rate (1.0E-6) is greater than the maximum value of uint32." plz help me
  2 个评论
Yao Li
Yao Li 2013-5-14
Why you set your sample time as large as 1e6?
Yao Li
Yao Li 2013-5-14
I think for the BLDC, the unit of the frequence of the input signal is kHz, thus, what you really need is a much smaller sample time. However, simulink can not generate this kind of signal or the simulation speed is too slow with a kHz frequency. Try to carry out HIL tests or use a reasonable frequency to verify your DC model first.

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