You may try to solve using the following steps:
2) Append a combinational logic to actually compare current simulation time with your time of interest.
3) Use an enabled subsystem to appropriately route the signal to output with output signal of step 2 as control signal to this block.
Here's an illustration of these steps:
As depicted in the scope, the signal (here sine signal is taken as an example) is routed to the output only in the time slot of interest.
