Errors : algebraic loop in use HDL simulink coder

Question

Pham Van Dung 2013-6-2

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https://ww2.mathworks.cn/matlabcentral/answers/77758-errors-algebraic-loop-in-use-hdl-simulink-coder

回答： Kiran Kintali 2023-3-28

Dear friends, when i convert one Simulink block to Verilog use HDL Simulink coder, i have this problem: *_ Failed Cannot connect to model; please try Update Diagram (Ctrl-D).

Cause:

Block diagram 'untitled' contains an algebraic loop. The algebraic loop solver is disabled because of the current setting for Algebraic loop option in the Diagnostics page of the Configuration Parameters Dialog_*

Can you give me some suggestions to solve this problem? Thanks so much!

Pham Van Dung

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Pham Van Dung 2013-6-7

编辑：Pham Van Dung 2013-6-7

thanks for helping

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Answer 1

Tim McBrayer 2013-6-3

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https://ww2.mathworks.cn/matlabcentral/answers/77758-errors-algebraic-loop-in-use-hdl-simulink-coder#answer_87518

The error message states you have an algebraic loop in your design. Basically, an algebraic loop is a path in your Simulink model that makes a loop, and has no delays in it. HDL Coder does not support code generated for designs with algebraic loops, as this will in general result in hardware that is unstable.

For more information about algebraic loops, see http://www.mathworks.com/support/solutions/en/data/1-16V6S/.

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Pham Van Dung 2013-6-7

Thanks Tim McBrayer for your answer!

I already fix the problem in algebraic loop. I use a delay block in my feedback and now the model is ok. But i have a new problem: When i convert to verilog and co-simulation with Modelsim, i have a error that i have posted before:

http://www.mathworks.com/matlabcentral/answers/74856-error-beetween-two-methods-simulink-and-verilog-after-convert-by-hdl-coder

It looks like the two waveforms are identical, but time-shifted.I already ask a question but nobody reply it.

Once again, i need your helping!

Thanks you so much!

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