HDL Coder Buffer Problem
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Hello everyone,
I am trying to update this subsystem (below) for HDL generation but I don't know how to replace the buffer. Someone can help me please ?
Thank you a lot
回答（1 个）
Kiran Kintali
2021-3-23
0 个投票
Can you attach the model? Thanks
6 个评论
Catteau Ophélie
2021-3-23
Kiran Kintali
2021-3-23
what is FFTLength and other variables needed to compile the model?
Do you need Spectrum Viewer (the enabled subsystem) as a part of DUT generating VHDL/Verilog through HDL Coder? If not, you should put it outside the DUT before generating HDL from the subsystem.
Catteau Ophélie
2021-3-23
Kiran Kintali
2021-3-23
I would like to know more about the requirements. HDL FFT block has bitreverse order support options. Have you considered using them?
Catteau Ophélie
2021-3-24
编辑：Catteau Ophélie
2021-3-24
Bharath Venkataraman
2021-3-26
You can use a bank of 8 RAM blocks and use an HDL counter block to create write addresses and another to create read addresses. You can write in serial order 0, 1, ..7, 8, ... and read in bit reversed order, or the other way around. Since you are processing 8 samples of data per cycle, you will need to write the 8 samples of data in a way that you are able to read the right 8 samples at a time on the read side. Rather than using the valid for an enabled subsystem, I suggest using it as a write enable input to the RAM blocks.
I am curious to know why you think the natural order output (uncheck the option Output in bit-reversed order) is not working correctly. There is logic in that block that implements the bit-reversal I mention above.
One other thing I want to mention is that it is not clear that your input is being generated and passed in correctly. You may want to generate all your input in MATLAB (as many samples as you want), then using the Signal From Workspace block to send it 8 samples at a time to the FFT HDL Optimized block.
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2021-3-23
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