you can try one of the basic example models with floating point and try to generte code and testbench. check documentation for floating point code generation and testbench related options.
>> sfir_single
% Generate HDL Coder for floating point model <================
>> makehdl('sfir_single/symmetric_fir')
### Generating HDL for 'sfir_single/symmetric_fir'.
### Using the config set for model sfir_single for HDL code generation parameters.
### Running HDL checks on the model 'sfir_single'.
### Begin compilation of the model 'sfir_single'...
### Applying HDL optimizations on the model 'sfir_single'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 42 cycles.
### Output port 2: 42 cycles.
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'sfir_single'.
### Working on sfir_single/symmetric_fir/nfp_add_single as hdlsrc\sfir_single\nfp_add_single.vhd.
### Working on sfir_single/symmetric_fir/nfp_mul_single as hdlsrc\sfir_single\nfp_mul_single.vhd.
### Working on sfir_single/symmetric_fir as hdlsrc\sfir_single\symmetric_fir.vhd.
### Generating package file hdlsrc\sfir_single\symmetric_fir_pkg.vhd.
### Code Generation for 'sfir_single' completed.
### Creating HDL Code Generation Check Report symmetric_fir_report.html
### HDL check for 'sfir_single' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
% Generate Test Bench <================
>> makehdltb('sfir_single/symmetric_fir')
### Begin TestBench generation.
### Generating HDL TestBench for 'sfir_single/symmetric_fir'.
### Begin compilation of the model 'sfir_single'...
### Begin compilation of the model 'gm_sfir_single'...
### Begin simulation of the model 'gm_sfir_single'...
### Collecting data...
### Generating test bench data file: hdlsrc\sfir_single\x_in.dat.
### Generating test bench data file: hdlsrc\sfir_single\y_out_expected.dat.
### Generating test bench data file: hdlsrc\sfir_single\delayed_xout_expected.dat.
### Working on symmetric_fir_tb as hdlsrc\sfir_single\symmetric_fir_tb.vhd.
### Generating package file hdlsrc\sfir_single\symmetric_fir_tb_pkg.vhd.
### HDL TestBench generation complete.
>>
